The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Aug. 10, 2014
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ching-Wen Hung, Tainan, TW;

Jia-Rong Wu, Kaohsiung, TW;

Tsung-Hung Chang, Yunlin County, TW;

Ching-Ling Lin, Kaohsiung, TW;

Yi-Hui Lee, Taipei, TW;

Chih-Sen Huang, Tainan, TW;

Yi-Wei Chen, Taichung, TW;

Chun-Hsien Lin, Tainan, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 23/485 (2013.01); H01L 23/535 (2013.01); H01L 29/665 (2013.01); H01L 29/785 (2013.01); H01L 23/53266 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.


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