The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Dec. 15, 2011
Nicolas Breil, Grenoble, FR;
Michael P. Chudzik, Danbury, CT (US);
Rishikesh Krishnan, Poughkeepsie, NY (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Unoh Kwon, Fishkill, NY (US);
Nicolas Breil, Grenoble, FR;
Michael P. Chudzik, Danbury, CT (US);
Rishikesh Krishnan, Poughkeepsie, NY (US);
Siddarth A. Krishnan, Peekskill, NY (US);
Unoh Kwon, Fishkill, NY (US);
GLOBALFOUNDRIES U.S. 2 LLC, Hopewell Junction, NY (US);
Abstract
A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.