The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2016
Filed:
Jun. 27, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Rahul N. Manepalli, Chandler, AZ (US);
Hamid R. Azimi, Chandler, AZ (US);
John S. Guzek, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 13/04 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 24/96 (2013.01); H05K 3/4682 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3114 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/96 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/181 (2013.01); H01L 2924/186 (2013.01); H05K 3/0097 (2013.01); H05K 3/4679 (2013.01); H05K 2201/09918 (2013.01); H05K 2203/1536 (2013.01);
Abstract
Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.