Dual depth trench-gated mos-controlled thyristor with well-defined turn-on characteristics

Abstract

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n− layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. Some of the gate regions are first gate regions that only extend into the p-well, and other ones of the gate regions are second gate regions that extend through the p-well and into the n− layer to create a vertical conducting channel when biased. The second gate regions increase the beta of the PNP transistor. When the first gate regions are biased, the base of the NPN transistor is narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The distributed second gate regions lower the minimum gate voltage needed to turn on the thyristor.