The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 05, 2016
Filed:
Oct. 21, 2014
Sandisk Technologies Inc., Plano, TX (US);
Masanori Tsutsumi, Yokkaichi, JP;
Hiroshi Sasaki, Yokkaichi, JP;
Hiroyuki Ogawa, Yokkaichi, JP;
Michiaki Sano, Ichinomiya, JP;
Masato Miyamoto, Yokkaichi, JP;
Kensuke Yamaguchi, Yokkaichi, JP;
Seiji Shimabukuro, Yokkaichi, JP;
SANDISK TECHNOLOGIES INC., Plano, TX (US);
Abstract
A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.