The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2016

Filed:

Aug. 31, 2012
Applicants:

Pravin K. Narwankar, Sunnyvale, CA (US);

Joe Griffith Cruz, San Jose, CA (US);

Arvind Sundarrajan, San Jose, CA (US);

Murali Narasimhan, San Jose, CA (US);

Subbalakshmi Sreekala, Sunnyvale, CA (US);

Victor Pushparaj, Sunnyvale, CA (US);

Inventors:

Pravin K. Narwankar, Sunnyvale, CA (US);

Joe Griffith Cruz, San Jose, CA (US);

Arvind Sundarrajan, San Jose, CA (US);

Murali Narasimhan, San Jose, CA (US);

Subbalakshmi Sreekala, Sunnyvale, CA (US);

Victor Pushparaj, Sunnyvale, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 21/768 (2006.01); A61Q 9/04 (2006.01); H01L 23/538 (2006.01); A61K 8/46 (2006.01); A61K 8/81 (2006.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); A61K 8/46 (2013.01); A61K 8/8182 (2013.01); A61Q 9/04 (2013.01); H01L 21/76843 (2013.01); H01L 23/5384 (2013.01); A61K 2800/884 (2013.01); B82Y 40/00 (2013.01); H01L 29/413 (2013.01); H01L 2924/0002 (2013.01); Y10S 977/742 (2013.01);
Abstract

An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode.


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