The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2016

Filed:

Apr. 07, 2014
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Fernando Gonzalez, Richardson, TX (US);

Chandra V. Mouli, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/401 (2006.01); G11C 11/405 (2006.01); G11C 11/408 (2006.01); H01L 27/108 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); G11C 11/409 (2006.01); H01L 27/07 (2006.01);
U.S. Cl.
CPC ...
G11C 11/401 (2013.01); G11C 11/405 (2013.01); G11C 11/408 (2013.01); G11C 11/409 (2013.01); H01L 27/108 (2013.01); H01L 27/10802 (2013.01); H01L 29/66666 (2013.01); H01L 29/7841 (2013.01); H01L 27/0705 (2013.01);
Abstract

A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell include forming the capacitor-less memory cell in an active area of a substantially physically isolated portion of a bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.


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