The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2016
Filed:
May. 02, 2014
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Lee-Chung Lu, Taipei, TW;
Yi-Kan Cheng, Taipei, TW;
Chung-Hsing Wang, Baoshan Township, TW;
Chen-Fu Huang, Kaohsiung, TW;
Hsiao-Shu Chao, Baoshan Township, TW;
Chin-Yu Chiang, New Taipei, TW;
Ho Che Yu, Zhubei, TW;
Chih Sheng Tsai, Taichung County, TW;
Shu Yi Ying, Taichung, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An embodiment is a method for providing an adjusted electronic representation of an integrated circuit layout, the method including using one or more processor, generating a timing performance of a path in a first netlist, identifying a first cell in the path that violates a timing performance parameter, and generating a plurality of derivative cells from a subsequent cell that is in the path after the first cell, where each derivative cell includes a variation of the subsequent cell. The method further includes in response to the identifying the first cell, replacing the subsequent cell with at least one of the plurality of derivative cells to generate a first modified netlist, where the variation of the at least one of the plurality of derivative cells reduces the violation of the timing performance parameter, and generating a final netlist based on the first modified netlist.