The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2016

Filed:

Dec. 03, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Lun Liu, Hsin-Chu, TW;

Chia-Chu Liu, Hsin-Chu, TW;

Kuei-Shun Chen, Hsin-Chu, TW;

Chung-Ming Wang, Hsin-Chu, TW;

Chie-Chieh Lin, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03F 1/38 (2012.01); G03F 1/00 (2012.01);
U.S. Cl.
CPC ...
G03F 1/38 (2013.01); G03F 1/00 (2013.01);
Abstract

A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.


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