The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Sep. 18, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Ling Wu, Singapore, SG;

Jianbo Yang, Singapore, SG;

Kian Hong Lim, Singapore, SG;

Sung Mun Jung, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 29/06 (2006.01); H01L 27/115 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0619 (2013.01); H01L 21/28273 (2013.01); H01L 21/76802 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11548 (2013.01); H01L 29/42324 (2013.01);
Abstract

A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.


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