The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 23, 2016

Filed:

Jan. 15, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Houssam W. Jomaa, San Diego, CA (US);

Omar J. Bchir, San Marcos, CA (US);

Milind P. Shah, San Diego, CA (US);

Manuel Aldrete, San Diego, CA (US);

Chin-Kwan Kim, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 21/563 (2013.01); H01L 24/81 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/27011 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/81464 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83192 (2013.01);
Abstract

Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (μm) or less.


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