The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 23, 2016
Filed:
Nov. 05, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Yi-Chuan Teng, Zhubei, TW;
Jung-Huei Peng, Jhubei, TW;
Shang-Ying Tsai, Pingzhen, TW;
Li-Min Hung, Longtan Township, TW;
Yao-Te Huang, Hsinchu, TW;
Chin-Yi Cho, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
In a wafer level chip scale packaging technique for MEMS devices, a deep trench is etched on a scribe line area between two CMOS devices of a CMOS substrate at first. After bonding of the CMOS substrate with a MEMS substrate, the deep trench is opened by thin-down process so that CMOS substrate is singulated while MEMS substrate is not (partial singulation). Electrical test pad on MEMS substrate is exposed and protection material can be filled through the deep trench around bonding layers. After filling the protection material, the wafer is diced to form packaged individual chips with protection from environment outside bonding layer.