Resistive memory apparatus and write-in method thereof

Abstract

A resistive memory apparatus and a write-in method thereof are provided. The memory controller provides unselected bit-lines and unselected word-lines both not coupled to a selected resistive memory cell respectively with a first bit-line voltage and a first word-line voltage in one of a setting duration and a resetting duration, wherein the first bit-line voltage is equal to a product of a writing-in voltage Vand (n−1)/n and the first word-line voltage is equal to V×1/n. The memory controller provides the unselected bit-lines not coupled to the selected resistive memory cell with a second bit-line voltage and the unselected word-lines not coupled to the selected resistive memory cell with a second word-line voltage in the other one of the setting duration and the resetting duration, wherein the second bit-line voltage is equal to V×1/n and the second word-line voltage is equal to V×(n−1)/n.