The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Oct. 30, 2014
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Ching-Ling Lin, Kaohsiung, TW;
Chih-Sen Huang, Tainan, TW;
Ching-Wen Hung, Tainan, TW;
Jia-Rong Wu, Kaohsiung, TW;
Tsung-Hung Chang, Yunlin County, TW;
Yi-Hui Lee, Taipei, TW;
Yi-Wei Chen, Taichung, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Science-Based Industrial Park, Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 23/535 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 23/535 (2013.01); H01L 21/0217 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/823475 (2013.01); H01L 29/78 (2013.01);
Abstract
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.