The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 16, 2016
Filed:
Jul. 25, 2014
Lakshminarayan Viswanathan, Phoenix, AZ (US);
Lakshmi N. Ramanathan, Sammamish, WA (US);
Audel A. Sanchez, Tempe, AZ (US);
Fernando A. Santos, Chandler, AZ (US);
Lakshminarayan Viswanathan, Phoenix, AZ (US);
Lakshmi N. Ramanathan, Sammamish, WA (US);
Audel A. Sanchez, Tempe, AZ (US);
Fernando A. Santos, Chandler, AZ (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.