The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2016

Filed:

Nov. 20, 2014
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-ken, JP;

Inventors:

Hiromu Arisaka, Nagano, JP;

Noriyoshi Shimizu, Nagano, JP;

Masato Tanaka, Nagano, JP;

Tetsuya Koyama, Nagano, JP;

Akio Rokugawa, Nagano, JP;

Assignee:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49838 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 25/105 (2013.01); H05K 1/0298 (2013.01); H05K 1/0313 (2013.01); H05K 1/113 (2013.01); H01L 23/3128 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/1023 (2013.01); H01L 2924/15174 (2013.01); H01L 2924/15311 (2013.01); H05K 2201/0137 (2013.01); H05K 2201/029 (2013.01);
Abstract

A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.


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