The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 02, 2016
Filed:
Aug. 20, 2014
Chih-fang Huang, Hsinchu, TW;
Tsung-yi Huang, Hsinchu, TW;
Chien-wei Chiu, Yunlin, TW;
Tsung-yu Yang, Kaohsiung, TW;
Ting-fu Chang, Taipei, TW;
Tsung-chieh Hsiao, Changhua, TW;
Ya-hsien Liu, Hsinchu, TW;
Po-chin Peng, Hsinchu, TW;
Chih-Fang Huang, Hsinchu, TW;
Tsung-Yi Huang, Hsinchu, TW;
Chien-Wei Chiu, Yunlin, TW;
Tsung-Yu Yang, Kaohsiung, TW;
Ting-Fu Chang, Taipei, TW;
Tsung-Chieh Hsiao, Changhua, TW;
Ya-Hsien Liu, Hsinchu, TW;
Po-Chin Peng, Hsinchu, TW;
RICHTEK TECHNOLOGY CORPORATION, Chupei, Hsinchu, TW;
Abstract
The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.