The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Mar. 30, 2014
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Yi-Hung Li, Hsinchu, TW;

Yen-Hsin Lai, Taipei, TW;

Ming-Shan Lo, Hsinchu, TW;

Shih-Chan Huang, Hsinchu County, TW;

Assignee:

eMemory Technology Inc., Hsinchu Science Park, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 29/788 (2006.01); H01L 21/336 (2006.01); G11C 16/04 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01); H01L 29/51 (2006.01); H01L 29/792 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66833 (2013.01); G11C 16/0416 (2013.01); G11C 16/0441 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11558 (2013.01); H01L 29/0649 (2013.01); H01L 29/42344 (2013.01); H01L 29/512 (2013.01); H01L 29/66545 (2013.01); H01L 29/788 (2013.01); H01L 29/7881 (2013.01); H01L 29/792 (2013.01); G11C 2216/10 (2013.01);
Abstract

According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.


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