The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Dec. 18, 2013
Applicants:

Robert L. Bristol, Portland, OR (US);

Kevin Lin, Chandler, AZ (US);

Kanwal Jit Singh, Hillsboro, OR (US);

Alan M. Myers, Beaverton, OR (US);

Richard E. Schenker, Portland, OR (US);

Inventors:

Robert L. Bristol, Portland, OR (US);

Kevin Lin, Chandler, AZ (US);

Kanwal Jit Singh, Hillsboro, OR (US);

Alan M. Myers, Beaverton, OR (US);

Richard E. Schenker, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/027 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/0274 (2013.01); H01L 21/31111 (2013.01); H01L 21/76802 (2013.01); H01L 21/76897 (2013.01); H01L 23/522 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate, the first layer having a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The integrated circuit also includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines of the second grating. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The integrated circuit also includes a region of dielectric material disposed between the metal lines of the first grating and the metal lines of the second grating, and in a same plane as upper portions of the dielectric lines of the first grating and lower portions of the dielectric lines of the second grating. The region of dielectric material is composed of a cross-linked photolyzable material.


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