The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2016

Filed:

Feb. 12, 2013
Applicant:

Stats Chippac, Ltd., Singapore, SG;

Inventors:

Reza A. Pagaila, Tangerang, ID;

KiYoun Jang, Kyoungki-do, KR;

HunTeak Lee, Kyoungki-do, KR;

Assignee:

STATS ChipPAC, Ltd., Singapore, SG;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49582 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 23/3107 (2013.01); H01L 24/29 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05001 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05111 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05639 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32057 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/451 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48249 (2013.01); H01L 2224/49109 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/83385 (2013.01); H01L 2224/92 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/0103 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01024 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.


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