The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 12, 2016
Filed:
Mar. 12, 2014
Intel Ip Corporation, Santa Clara, CA (US);
Vianney Choserot, Antibes, FR;
Loubna Hannati, Roquefort les pins, FR;
Nabil Badereddine, Grasse, FR;
Christophe Chanussot, Antibes, FR;
INTEL IP CORPORATION, Santa Clara, CA (US);
Abstract
Embodiments of design-for-test (DFT) apparatuses and related techniques are disclosed herein. In some embodiments, a DFT apparatus may include a static random access memory (SRAM) cell, read/write/decoder (R/W/decoder) circuitry to provide a nominal word line (WL) voltage and a nominal bit line (BL) voltage for application to the SRAM cell during accesses. The DFT apparatus may also include test circuitry having an activated state and a deactivated state. When the test circuitry is in the activated state, in some embodiments, the WL voltage and/or the BL voltage applied to the SRAM cell may be different from the nominal voltages provided by the R/W/decoder circuitry. The R/W/decoder circuitry may be operated to perform accesses to the SRAM cell while the test circuitry is in the activated state. Other embodiments may be disclosed and/or claimed.