The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Oct. 28, 2011
Applicants:

David Edward Fisch, Pleasanton, CA (US);

Michael Curtis Parris, San Jose, CA (US);

Inventors:

David Edward Fisch, Pleasanton, CA (US);

Michael Curtis Parris, San Jose, CA (US);

Assignee:

INVENSAS CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/4236 (2013.01); H01L 29/42336 (2013.01); H01L 29/42368 (2013.01); H01L 29/66181 (2013.01); H01L 29/66825 (2013.01); H01L 29/785 (2013.01); H01L 29/7881 (2013.01); H01L 29/945 (2013.01); H01L 27/11558 (2013.01); H01L 29/7889 (2013.01);
Abstract

Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.


Find Patent Forward Citations

Loading…