The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Nov. 06, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

William L. Barber, Bampton, GB;

Keith Pinson, Swindon, GB;

Andrew P. Collins, Hillsboro, OR (US);

Boping Wu, Folsom, CA (US);

Isaac Ali, Bristol, GB;

Colin L. Perry, Swindon, GB;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/22 (2006.01); H02H 9/04 (2006.01); H05K 1/02 (2006.01); H01L 23/50 (2006.01);
U.S. Cl.
CPC ...
H02H 9/04 (2013.01); H01L 23/50 (2013.01); H05K 1/025 (2013.01); H05K 1/0231 (2013.01); H01L 2924/0002 (2013.01); H05K 2201/09672 (2013.01);
Abstract

In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.


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