The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Jul. 29, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Renata Camillo-Castillo, Essex Junction, VT (US);

Santosh Sharma, Essex Junction, VT (US);

Yun Shi, South Burlington, VT (US);

Anthony K. Stamper, Williston, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/30604 (2013.01); H01L 21/76224 (2013.01); H01L 29/0649 (2013.01); H01L 29/0865 (2013.01); H01L 29/0882 (2013.01); H01L 29/1095 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7835 (2013.01);
Abstract

Disclosed are a field effect transistor (FET) (e.g., a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET)) and a method of forming the FET. In the FET, an etch stop pad is on a semiconductor substrate (e.g., a P-type silicon substrate). A semiconductor layer (e.g., a silicon layer) is also on the substrate and extends laterally over the etch stop pad. A first well region (e.g., an N-well region) extends through the semiconductor layer into the substrate such that it contains the etch stop pad. A second well region (e.g., a P-well region) is in the first well region aligned above the etch stop pad. A source region (e.g., a N-type source region) is in the second well region. A buried isolation region (e.g., a buried air-gap isolation region) is within the first well region aligned below the etch stop pad so as to limit vertical capacitor formation.


Find Patent Forward Citations

Loading…