The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2015
Filed:
Jul. 12, 2013
Globalfoundries Inc., Grand Cayman, KY;
Kangguo Cheng, Schenectady, NY (US);
Eric C. Harley, Lagrangeville, NY (US);
Terence B. Hook, Jericho, VT (US);
Ali Khakifirooz, Mountain View, CA (US);
Henry K. Utomo, Newburgh, NY (US);
Reinaldo A. Vega, Wappingers Falls, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A semiconductor fin suspended above a top surface of a semiconductor layer and supported by a gate structure is formed. An insulator layer is formed between the top surface of the semiconductor layer and the gate structure. A gate spacer is formed, and physically exposed portions of the semiconductor fin are removed by an anisotropic etch. Subsequently, physically exposed portions of the insulator layer can be etched with a taper. Alternately, a disposable spacer can be formed prior to an anisotropic etch of the insulator layer. The lateral distance between two openings in the dielectric layer across the gate structure is greater than the lateral distance between outer sidewalls of the gate spacers. Selective deposition of a semiconductor material can be performed to form raised active regions.