The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2015
Filed:
Aug. 05, 2011
Gang Wang, St. Peters, MO (US);
Matty Caymax, Leuven, BE;
Maarten Leys, Eindhoven, NL;
Wei-e Wang, Overijse, BE;
Niamh Waldron, Leuven, BE;
Gang Wang, St. Peters, MO (US);
Matty Caymax, Leuven, BE;
Maarten Leys, Eindhoven, NL;
Wei-e Wang, Overijse, BE;
Niamh Waldron, Leuven, BE;
IMEC, Leuven, BE;
Katholieke Universiteit Leuven, KU Leuven R&D, Leuven, BE;
Abstract
Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface. The method further comprises at least partially filling the recessed region with a III-V compound semiconductor material overlaying the surface.