The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Dec. 28, 2011
Applicants:

Dongping Wu, Shanghai, CN;

Cheng HU, Shanghai, CN;

Lun Zhu, Shanghai, CN;

Zhiwei Zhu, Shanghai, CN;

Shili Zhang, Uppsala, SE;

Wei Zhang, Shanghai, CN;

Inventors:

Dongping Wu, Shanghai, CN;

Cheng Hu, Shanghai, CN;

Lun Zhu, Shanghai, CN;

Zhiwei Zhu, Shanghai, CN;

Shili Zhang, Uppsala, SE;

Wei Zhang, Shanghai, CN;

Assignee:

FUDAN UNIVERSITY, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 29/04 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28008 (2013.01); H01L 21/2815 (2013.01); H01L 21/28097 (2013.01); H01L 21/28105 (2013.01); H01L 21/28518 (2013.01); H01L 29/04 (2013.01); H01L 29/4975 (2013.01); H01L 29/6659 (2013.01); H01L 29/66575 (2013.01); H01L 29/66659 (2013.01); H01L 29/7835 (2013.01); H01L 21/26586 (2013.01);
Abstract

An asymetric gate MOS device is disclosed. The gate is a metal gate, and the metal gate has a different work function on the source side from that on the drain side of the MOS device, so that the overall performance parameters of the MOS device are more optimized. A method of making an asymetric gate MOS device is also disclosed. In the method, dopant ions are implanted into the gate of the MOS device, so as to cause the gate to have a different work function on the source side from that on the drain side of the MOS device. As a result, the overall performance parameters of the MOS device are more optimized. The method can be easily implemented.


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