The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
Jan. 15, 2014
Applicants:
Woo Jin Kim, Seoul, KR;
Sun Jae Kim, Seoul, KR;
Chung Lyul Ahn, Chunng-ju si, KR;
Hyeon Yi Kang, Tongyeong-si, KR;
Inventors:
Woo Jin Kim, Seoul, KR;
Sun Jae Kim, Seoul, KR;
Chung Lyul Ahn, Chunng-ju si, KR;
Hyeon Yi Kang, Tongyeong-si, KR;
Assignee:
STATS ChipPAC Ltd., Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 21/52 (2006.01); H01L 23/12 (2006.01); H01L 23/16 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76804 (2013.01); H01L 23/5226 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 21/563 (2013.01); H01L 23/12 (2013.01); H01L 23/16 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/3157 (2013.01); H01L 2225/06548 (2013.01);
Abstract
An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate; a device attached on a top surface of the substrate; a mold encapsulating the device, the mold having a through via and a recessed pattern characterized by being formed in a single process; and a conductive via in the through via and a conductive pattern in the recessed pattern characterized by being formed in another single process.