The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
Mar. 26, 2012
Applicants:
Mark Helm, Santa Cruz, CA (US);
Jung Sheng Hoei, Fremont, CA (US);
Aaron Yip, Santa Clara, CA (US);
Dzung Nguyen, Freemont, CA (US);
Inventors:
Mark Helm, Santa Cruz, CA (US);
Jung Sheng Hoei, Fremont, CA (US);
Aaron Yip, Santa Clara, CA (US);
Dzung Nguyen, Freemont, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 8/14 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2006.01); G11C 5/02 (2006.01); G11C 5/12 (2006.01); G11C 13/00 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 5/025 (2013.01); G11C 5/12 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 13/0002 (2013.01); G11C 13/0004 (2013.01); G11C 13/0023 (2013.01); G11C 16/24 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/1052 (2013.01); H01L 27/11526 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); Y10T 29/49155 (2015.01);
Abstract
An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.