The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Jun. 16, 2014
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/11 (2006.01); H01L 27/02 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/76895 (2013.01); H01L 21/823475 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 27/1104 (2013.01); H01L 29/0688 (2013.01); H01L 29/165 (2013.01); H01L 29/7848 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01);
Abstract
The present disclosure relates to a method for fabricating a butted a contact arrangement configured to couple two transistors, wherein an active region of a first transistor is coupled to a gate of a second transistor. The gate of the second transistor is formed from a gate material which comprises a dummy gate of the first transistor, and is configured to straddle a boundary between the active region of the first transistor and an isolation layer formed about the first transistor. The butted a contact arrangement results in a decreased contact resistance for the butted contact as compared to previous methods.