The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2015
Filed:
Sep. 21, 2009
Jeong-do Ryu, Gyeonggi-do, KR;
Dong-chan Kim, Gyeonggi-do, KR;
Seong-hoon Jeong, Gyeonggi-do, KR;
Si-young Choi, Gyeonggi-do, KR;
Yu-gyun Shin, Gyeonggi-do, KR;
Tai-su Park, Gyeonggi-do, KR;
Jong-ryeol Yoo, Gyeonggi-do, KR;
Jong-hoon Kang, Gyeonggi-do, KR;
Jeong-Do Ryu, Gyeonggi-do, KR;
Dong-Chan Kim, Gyeonggi-do, KR;
Seong-Hoon Jeong, Gyeonggi-do, KR;
Si-Young Choi, Gyeonggi-do, KR;
Yu-Gyun Shin, Gyeonggi-do, KR;
Tai-Su Park, Gyeonggi-do, KR;
Jong-Ryeol Yoo, Gyeonggi-do, KR;
Jong-Hoon Kang, Gyeonggi-do, KR;
Abstract
A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.