The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

May. 29, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Chih-Liang Chen, Hsinchu, TW;

Helen Shu-Hui Chang, Baoshan Township, TW;

Charles Chew-Yuen Young, Cupertino, CA (US);

Jiann-Tyng Tzeng, Hsin Chu, TW;

Kam-Tou Sio, Zhubei, TW;

Wei-Cheng Lin, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41775 (2013.01); H01L 21/823456 (2013.01); H01L 27/088 (2013.01); H01L 29/42356 (2013.01);
Abstract

A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a first contact having first contact dimensions that are relative to first gate dimensions of at least one of a first gate or a second gate, where relative refers to a specific relationship between the first contact dimensions and the first gate dimensions. The first contact is between the first gate and the second gate. The first contact having the first contact dimensions relative to the first gate dimensions has lower resistance with little to no increased capacitance, as compared to a semiconductor arrangement having first contact dimensions not in accordance with the specific relationship. The semiconductor arrangement having the lower resistance with little to no increased capacitance exhibits at least one of improved performance or reduced power requirements than a semiconductor arrangement that does not have such lower resistance with little to no increased capacitance.


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