The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Sep. 27, 2013
Applicants:

Kyunghwan Kim, Seoul, KR;

Deokkyung Yang, Hanam-si, KR;

Seonghun Mun, Bucheon-si, KR;

Keochang Lee, Icheon-si, KR;

Inventors:

KyungHwan Kim, Seoul, KR;

DeokKyung Yang, Hanam-si, KR;

SeongHun Mun, Bucheon-si, KR;

KeoChang Lee, Icheon-si, KR;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 21/561 (2013.01);
Abstract

Semiconductor packages with multiple substrates can incorporate apertures or slots between devices to minimize or reduce formation of defects during a molding process. The apertures or slots can be formed adjacent a top substrate in alignment with removable regions adjacent a bottom substrate whereby the apertures or slots can facilitate outflow of materials from cavities between the substrates. The apertures or slots may subsequently be removed in conjunction with the removable regions during a singulation process thereby producing the desired semiconductor packages with improved device reliability and yield.


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