The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Dec. 06, 2013
Applicant:
Sandisk 3d Llc, Milpitas, CA (US);
Inventors:
Akira Nakada, Yokkaichi Mie, JP;
Michiaki Sano, Aichi ken, JP;
Naohito Yanagida, Yokkaichi Mie, JP;
Teruyuki Mine, Yokkaichi Mie, JP;
Assignee:
SanDisk 3D LLC, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 27/115 (2013.01); H01L 27/249 (2013.01); H01L 27/2454 (2013.01); H01L 29/42376 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01);
Abstract
A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.