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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9177888 B1

PDFFull Text
Date of Patent:
Nov. 03, 2015

Filed:

Dec. 01, 2014

Electrically isolated power semiconductor package with optimized layout

Applicant:

Ixys Corporation, Milpitas, CA (US);

Inventors:

Thomas Spann, Fuerth, DE;

Holger Ostmann, Rodgau, DE;

Kang Rim Choi, Cupertino, CA (US);

Assignee:

IXYS Corporation, Milpitas, CA (US);

Attorneys:

Imperium Patent Works

Amir V. Adibi

Primary Examiner:

Chuong A Luu

Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 23/40 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/52 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4006 (2013.01); H01L 21/52 (2013.01); H01L 21/56 (2013.01); H01L 23/3107 (2013.01); H01L 23/3157 (2013.01); H01L 23/3735 (2013.01); H01L 23/4334 (2013.01); H01L 23/49541 (2013.01); H01L 23/49562 (2013.01); H01L 23/49575 (2013.01); H01L 24/97 (2013.01); H01L 21/565 (2013.01); H01L 2023/405 (2013.01); H01L 2023/4031 (2013.01); H01L 2023/4087 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/49113 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13034 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15747 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/19107 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper ('DBC') substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

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