The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Jun. 29, 2007
Applicants:
Chien-ming Sung, Tainan, TW;
Simon Wang, Tainan, TW;
Jia-ren Chen, Tainan, TW;
Henry Lo, Hsin-Chu, TW;
Chen-hua Yu, Hsin-Chu, TW;
Jean Wang, Hsin-Chu, TW;
Kewei Zuo, Yonghe, TW;
Inventors:
Chien-Ming Sung, Tainan, TW;
Simon Wang, Tainan, TW;
Jia-Ren Chen, Tainan, TW;
Henry Lo, Hsin-Chu, TW;
Chen-Hua Yu, Hsin-Chu, TW;
Jean Wang, Hsin-Chu, TW;
Kewei Zuo, Yonghe, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/677 (2006.01); H01L 21/673 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/67393 (2013.01); H01L 21/67017 (2013.01); H01L 21/67161 (2013.01); H01L 21/67703 (2013.01); Y10S 414/139 (2013.01);
Abstract
A semiconductor manufacturing line includes an inert environment selected from the group consisting essentially of an inert airtight wafer holder, an inert wafer transport channel, an inert production tool, an inert clean room, and combinations thereof.