The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2015
Filed:
Mar. 31, 2011
Pulugurtha Markondeya Raj, Tucker, GA (US);
Nitesh Kumbhat, Atlanta, GA (US);
Venkatesh Sundaram, Alpharetta, GA (US);
Rao R. Tummala, Greensboro, GA (US);
Pulugurtha Markondeya Raj, Tucker, GA (US);
Nitesh Kumbhat, Atlanta, GA (US);
Venkatesh Sundaram, Alpharetta, GA (US);
Rao R. Tummala, Greensboro, GA (US);
Georgia Tech Research Corporation, Atlanta, GA (US);
Abstract
The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.