Self-adaptive composite tunneling field effect transistor and method for fabricating the same

Abstract

The present invention provides a tunneling field effect transistor and a method for fabricating the same which refer to a field effect transistor logic device and circuit in a CMOS ultra-large integrated circuit (ULSI). The inventive concept of the invention lies in that, in a case of an N-type transistor, a side portion of a doped source region adjacent to an edge of the control gate is further implanted with P+ impurities on a basis of the doped source region being initially doped N− impurities, so that the initial N− impurities in the implanted portion are completely compensated by the P+ impurities, and in a case of a P-type transistor, a side portion of the doped source region adjacent to an edge of the control gate is implanted with N+ impurities on a basis of the doped source region being initially doped P− impurities, so that the initial P− impurities in the implanted portion are completely compensated by the N+ impurities. In the transistor, the source region is implanted twice with different doping concentrations, such that a large current characteristic of the MOSFET can be effectively combined to increase an on-state current of the transistor, and also, the threshold adjustment for the MOSFET portion and the TFET portion of the transistor can be achieved in a self-adaptive way.