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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9171795 B1

PDFFull Text
Date of Patent:
Oct. 27, 2015

Filed:

Dec. 01, 2014

Integrated circuit packaging system with embedded component and method of manufacture thereof

Applicants:

Dong Ju Jeon, Seoul, KR;

Kyounghee Park, Seoul, KR;

Youngdal Roh, Icheon-si, KR;

Jinhee Jung, Busan, KR;

Inventors:

Dong Ju Jeon, Seoul, KR;

KyoungHee Park, Seoul, KR;

YoungDal Roh, Icheon-si, KR;

JinHee Jung, Busan, KR;

Assignee:

STATS ChipPAC Ltd., Singapore, SG;

Attorney:

Ishimaru & Associates LLP

Primary Examiner:

Alonzo Chambliss

Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 23/04 (2006.01); H05K 1/18 (2006.01); H01L 23/498 (2006.01); H01L 21/52 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49861 (2013.01); H01L 21/481 (2013.01); H01L 21/4803 (2013.01); H01L 21/486 (2013.01); H01L 21/4821 (2013.01); H01L 21/52 (2013.01); H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 23/5386 (2013.01); H01L 21/76804 (2013.01); H01L 25/0657 (2013.01);
Abstract

An integrated circuit packaging system, and a method of manufacture of an integrated circuit packaging system thereof, including: an embedding material on a component; a mask layer on the embedding material; a buried pattern in the mask layer, the outer surface of the buried pattern coplanar with the outer surface of the mask layer, the buried pattern electrically connected to the component; a patterned dielectric on a portion of the buried pattern; and an integrated circuit die on the buried pattern.

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