The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Feb. 15, 2013
Applicant:

Globalfoundries, Inc., Grand Cayman, KY (US);

Inventors:

Sohan Mehta, Saratoga Springs, NY (US);

Norman Chen, Poughkeepsie, NY (US);

Yuyang Sun, Wappingers Falls, NY (US);

Matthew Herrick, Mechanicville, NY (US);

Shyam Pal, Clifton Park, NY (US);

Jeong Soo Kim, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/308 (2006.01); G03F 7/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/308 (2013.01); G03F 7/0035 (2013.01);
Abstract

Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.


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