The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Aug. 09, 2013
Applicants:

Stmicroelectronics, Inc., Coppell, TX (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Nicolas Loubet, Guilderland, NY (US);

Prasanna Khare, Schenectady, NY (US);

Jin Cho, Palo Alto, CA (US);

Assignees:

STMICROELECTRONICS, INC., Coppell, TX (US);

GLOBALFOUNDRIES, INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.


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