The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Oct. 21, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Hanyi Ding, Colchester, VT (US);

Richard S. Graf, Gray, ME (US);

Gary R. Hill, Essex Junction, VT (US);

Wayne H. Woods, Jr., Burlington, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/492 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5225 (2013.01); H01L 23/66 (2013.01); H01L 24/09 (2013.01); H01L 22/12 (2013.01); H01L 22/14 (2013.01); H01L 23/3114 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16055 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/1713 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/1532 (2013.01); H01L 2924/2076 (2013.01);
Abstract

Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.


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