The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Dec. 14, 2012
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Bi-Ming Yen, Hsinchu, TW;

Tsai-Chun Li, Hisnchu, TW;

Chun-Ming Hu, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31116 (2013.01); H01L 21/31138 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01);
Abstract

A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.


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