The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Jul. 02, 2009
Applicants:

Vassil Antonov, Boise, ID (US);

Vishwanath Bhat, Boise, ID (US);

Inventors:

Vassil Antonov, Boise, ID (US);

Vishwanath Bhat, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01G 4/00 (2006.01); H01G 5/00 (2006.01); H01G 7/00 (2006.01); H01G 9/00 (2006.01); H01G 13/00 (2013.01); H01B 13/00 (2006.01); C23F 1/00 (2006.01); C23F 3/00 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02356 (2013.01); H01L 21/02175 (2013.01); H01L 21/3105 (2013.01); H01L 28/65 (2013.01);
Abstract

A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuOis deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuOand the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuOin physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.


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