The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
May. 17, 2011
Reynaldo CO, Scotts Valley, CA (US);
Jeffrey S. Leal, Scotts Valley, CA (US);
Suzette K. Pangrle, Cupertino, CA (US);
Scott Mcgrath, Scotts Valley, CA (US);
Deann Eileen Melcher, San Jose, CA (US);
Keith L. Barrie, Capitola, CA (US);
Grant Villavicencio, Scotts Valley, CA (US);
Elmer M. Del Rosario, San Jose, CA (US);
John R. Bray, San Jose, CA (US);
Reynaldo Co, Scotts Valley, CA (US);
Jeffrey S. Leal, Scotts Valley, CA (US);
Suzette K. Pangrle, Cupertino, CA (US);
Scott McGrath, Scotts Valley, CA (US);
DeAnn Eileen Melcher, San Jose, CA (US);
Keith L. Barrie, Capitola, CA (US);
Grant Villavicencio, Scotts Valley, CA (US);
Elmer M. del Rosario, San Jose, CA (US);
John R. Bray, San Jose, CA (US);
Invensas Corporation, San Jose, CA (US);
Abstract
Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.