The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2015

Filed:

Mar. 14, 2013
Applicants:

Corbin Champion, Tigard, OR (US);

John R. Pane, Tigard, OR (US);

Mark B. Donahue, Sherwood, OR (US);

Inventors:

Corbin Champion, Tigard, OR (US);

John R. Pane, Tigard, OR (US);

Mark B. Donahue, Sherwood, OR (US);

Assignee:

Teradyne, Inc., North Reading, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/3183 (2006.01); G06F 9/32 (2006.01); G01R 31/319 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318307 (2013.01); G01R 31/31919 (2013.01); G06F 9/322 (2013.01); G01R 31/3177 (2013.01); G01R 31/31903 (2013.01); G01R 31/31917 (2013.01);
Abstract

According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths.


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