The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 01, 2015

Filed:

Dec. 29, 2011
Applicants:

Bin HU, Portland, OR (US);

Vivek K. Singh, Portland, OR (US);

Sungwon Kim, Portland, OR (US);

Chulwoo OH, Hillsboro, OR (US);

Mehmet E. Yavuz, Hillsboro, OR (US);

Inventors:

Bin Hu, Portland, OR (US);

Vivek K. Singh, Portland, OR (US);

Sungwon Kim, Portland, OR (US);

Chulwoo Oh, Hillsboro, OR (US);

Mehmet E. Yavuz, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/68 (2012.01); G03F 1/26 (2012.01); G03F 1/70 (2012.01);
U.S. Cl.
CPC ...
G03F 1/68 (2013.01); G03F 1/26 (2013.01); G03F 1/70 (2013.01);
Abstract

Improved mask layout patterns are described for closely spaced primitives in phase shift photolithography masks. In one example, at least a portion of a photolithography mask layout is decomposed into primitives. Jogs are identified from among the primitives, the jogs being characterized by three adjacent corners. E-fields are determined for the identified jogs and are applied to synthesize an electric field at a substrate. The mask layout is corrected using the synthesized electric field and a printed wafer pattern is calculated.


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