The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 25, 2015
Filed:
Sep. 14, 2011
King-yuen Wong, Hsin-Chu, TW;
Chia-yu LU, Hsin-Chu, TW;
Chien-chang Su, Kaohsiung, TW;
Yen-chun Lin, Hsin-Chu, TW;
Yi-fang Pai, Hsin-Chu, TW;
Da-wen Lin, Hsin-Chu, TW;
King-Yuen Wong, Hsin-Chu, TW;
Chia-Yu Lu, Hsin-Chu, TW;
Chien-Chang Su, Kaohsiung, TW;
Yen-Chun Lin, Hsin-Chu, TW;
Yi-Fang Pai, Hsin-Chu, TW;
Da-Wen Lin, Hsin-Chu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.