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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9093302 B1

PDFFull Text
Date of Patent:
Jul. 28, 2015

Filed:

Nov. 13, 2013

Methods of forming substantially self-aligned isolation regions on finfet semiconductor devices and the resulting devices

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Vimal K. Kamineni, Albany, NY (US);

Abner F. Bello, Clifton Park, NY (US);

Nicholas V. LiCausi, Watervliet, NY (US);

Wenhui Wang, Clifton Park, NY (US);

Michael Wedlake, Albany, NY (US);

Jason R. Cantone, Mechanicville, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:

Amerson Law Firm, PLLC

Primary Examiner:

Phat X Cao

Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 27/108 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 27/10879 (2013.01); H01L 27/1211 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/66787 (2013.01); H01L 29/66795 (2013.01);
Abstract

One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

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