The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2015
Filed:
Aug. 21, 2013
Asanga H. Perera, West Lake Hills, TX (US);
Cheong Min Hong, Austin, TX (US);
Sung-taeg Kang, Austin, TX (US);
Byoung W. Min, Austin, TX (US);
Jane A. Yater, Austin, TX (US);
Asanga H. Perera, West Lake Hills, TX (US);
Cheong Min Hong, Austin, TX (US);
Sung-Taeg Kang, Austin, TX (US);
Byoung W. Min, Austin, TX (US);
Jane A. Yater, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.